Xilinx SDNet 2018.2

Xilinx SDNet 2018.2 | 415.3 mb

Xilinx is pleased to announce the availability of SDNet 2018.2. This plane builder generates systems that can be programmed for a wide range of packet processing functions, from simple packet classification to complex packet editing.

SDNet Compiler Release Notes - UG1018 (v2018.2) October 12, 2018:

- Minor updates to P4-SDNet.
- PX system building now flattens hierarchical design during compilation to fix an issue where systems could have tuple connections that could bypass subsystems.
- Fixed issue with Vivado® Design Suite simulation scripts.
- Updated XPM compatibility for newer versions of Vivado tools.
- Includes additional P4 example designs.
Known Issues
- Xilinx recommends using a common clock to drive the clk_lookup and clk_control inputs on lookup engines.
- For testbench simulation convenience, SDNet copies a version Vivado's XPM IP (xpm_cdc.sv, xpm_memory.sv, and xpm_fifo.sv) into the same directory as the Verilog sources. However, in the case of running the Vivado implementation tools on the design, it might be necessary to either remove or replace these files before packaging the IP to avoid conflicts with other versions of these files. Vivado Design Suite provides its version of these files within the Xilinx\Vivado\2018.x\data\ip\xpm subdirectories.

About Xilinx SDNet. The SDNet Development Environment for networking, in conjunction with Xilinx FPGA and SoC devices, allows for the creation of next-generation hardware-accelerated software-defined networks.

SDNet supports packet processing functionality with high throughput and low latency. It allows for game-changing differentiation through software-programmable data plane hardware with content intelligence that dynamically collaborates with control plane software. This addresses the performance, flexibility, and security challenges of modern content-oriented, intent-based, and zero-touch, networking.

SDNet finds applications in data plane acceleration across network switching, network slicing, data center networking, and multi-access edge computing (MEC), including Software Defined Networking (SDN) with Network Functions Virtualization (NFV) and network security (IPSec, SSL, NGFW etc.) use cases.

About Xilinx. Xilinx is the leading provider of All Programmable FPGAs, SoCs, MPSoCs, and 3D ICs. Xilinx uniquely enables applications that are both software defined and hardware optimized - powering industry advancements in Cloud Computing, SDN/NFV, Video/Vision, Industrial IoT, and 5G Wireless.

Supported Architectures: x64
Language: english
System Requirements: PC / Linux
Software Prerequisites: For Windows operating systems, Vivado Design Suite 2017.3 or later is required for RTL simulation.

Home Page :
DOWNLOAD
(Buy premium account for maximum speed and resuming ability)